1. Field of the Invention
The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly, to a field effect transistor and a method of manufacturing the same with reduced gate sheet resistance.
2. Discussion of the Related Art
In general, a highly integrated semiconductor device includes a large number of field effect transistors. In order to increase the degree of integration, the field effect transistors are formed with a very small size. As the transistor size becomes smaller, the sheet resistances of source/drain and gate of the field effect transistor increase. This results in a delay of signal transfer in the integrated circuit. If the sheet resistances related to the source/drain and the gate decrease, the signal transfer time can be reduced. Another problem caused by high integration is that a contact resistance increases as the contact region of the gate, source/drain, and an interconnection layer decreases. This also delays the signal transfer time.
Hereinafter, a conventional field effect transistor and a method of manufacturing the same will be described with reference to FIG. 1 and FIGS. 2a to 2f.
As shown in FIG. 1, the conventional field effect transistor includes a silicon substrate 10, a field oxide film 11 formed on the silicon substrate 10, a gate formed on an active region of the silicon substrate including a polysilicon film 13 and a silicide film 14, sidewall spacers 16 formed at both sides of the gate, lightly doped drain (LDD) regions 15 formed on the surface of the silicon substrate 10 below the sidewall spacers 16, and source/drain regions 17 formed to be in contact with the LDD regions 15. The source/drain regions 17 extend over the surface of the silicon substrate 10 at respective sides of the sidewall spacers 16.
A method of manufacturing the above field effect transistor will now be described with reference to FIGS. 2a to 2f. As shown in FIG. 2a, a field oxide film 101 is formed on a P-type silicon substrate 100. A gate insulating film 102, a polysilicon film 103 and a silicide film 104 are successively stacked on the entire surface of the P-type silicon substrate 100.
As shown in FIG. 2b, through a photo/etching process utilizing a gate mask, the silicide film 104 and polysilicon film 103 are sequentially patterned to form gate electrodes 103a and 104a. As shown in FIG. 2c, using the gate electrode as a mask, an ion implantation with a low concentration is carried out to form n.sup.- LDD regions 105.
As shown in FIG. 2d, an insulating film 106 is deposited over the entire surface of the silicon substrate 100. As shown in FIG. 2e, an anisotropic etching process is carried out on the insulating film 106 to form sidewall spacers 106a at both sides of the gate electrodes 103a and 104a. As shown in FIG. 2f, source/drain regions 107 are formed at the sides of the n.sup.- LDD regions 105.
According to the aforementioned conventional method, it is difficult to form a gate with a short gate length. In addition, the LDD region is unnecessarily formed in the source region.
This leads to a deterioration of the current characteristics as the resistance increases. Furthermore, since a silicide layer is used to reduce the resistance of the gate, if the gate length is short, the resistance reducing effect due to the silicide layer is lessened.